/* register offset define */
#define QSFP_FRONT_LOW_POWER_REG    0x60
#define QSFP_REAR_LOW_POWER_REG     0x61
#define QSFP_FRONT_RESET_REG        0x70
#define QSFP_REAR_RESET_REG         0x71
#define QSFP_FRONT_PRESENT_REG      0x80
#define QSFP_REAR_PRESENT_REG       0x81
#define QSFP_FRONT_INT_REG          0x90
#define QSFP_REAR_INT_REG           0x91
#define QSFP_RESET                  1

unsigned char qsfp_low_power_regs[33][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0x60, 0x01},
    {0x60, 0x02},
    {0x60, 0x04},
    {0x60, 0x08},
    {0x60, 0x10},
    {0x60, 0x20},
    {0x60, 0x40},
    {0x60, 0x80},
    {0x61, 0x01},
    {0x61, 0x02},
    {0x61, 0x04},
    {0x61, 0x08},
    {0x61, 0x10},
    {0x61, 0x20},
    {0x61, 0x40},
    {0x61, 0x80},
    {0x60, 0x01},
    {0x60, 0x02},
    {0x60, 0x04},
    {0x60, 0x08},
    {0x60, 0x10},
    {0x60, 0x20},
    {0x60, 0x40},
    {0x60, 0x80},
    {0x61, 0x01},
    {0x61, 0x02},
    {0x61, 0x04},
    {0x61, 0x08},
    {0x61, 0x10},
    {0x61, 0x20},
    {0x61, 0x40},
    {0x61, 0x80}
};

unsigned char qsfp_reset_regs[33][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0x70, 0x01},
    {0x70, 0x02},
    {0x70, 0x04},
    {0x70, 0x08},
    {0x70, 0x10},
    {0x70, 0x20},
    {0x70, 0x40},
    {0x70, 0x80},
    {0x71, 0x01},
    {0x71, 0x02},
    {0x71, 0x04},
    {0x71, 0x08},
    {0x71, 0x10},
    {0x71, 0x20},
    {0x71, 0x40},
    {0x71, 0x80},
    {0x70, 0x01},
    {0x70, 0x02},
    {0x70, 0x04},
    {0x70, 0x08},
    {0x70, 0x10},
    {0x70, 0x20},
    {0x70, 0x40},
    {0x70, 0x80},
    {0x71, 0x01},
    {0x71, 0x02},
    {0x71, 0x04},
    {0x71, 0x08},
    {0x71, 0x10},
    {0x71, 0x20},
    {0x71, 0x40},
    {0x71, 0x80}
};

unsigned char qsfp_present_regs[33][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0x80, 0x01},
    {0x80, 0x02},
    {0x80, 0x04},
    {0x80, 0x08},
    {0x80, 0x10},
    {0x80, 0x20},
    {0x80, 0x40},
    {0x80, 0x80},
    {0x81, 0x01},
    {0x81, 0x02},
    {0x81, 0x04},
    {0x81, 0x08},
    {0x81, 0x10},
    {0x81, 0x20},
    {0x81, 0x40},
    {0x81, 0x80},
    {0x80, 0x01},
    {0x80, 0x02},
    {0x80, 0x04},
    {0x80, 0x08},
    {0x80, 0x10},
    {0x80, 0x20},
    {0x80, 0x40},
    {0x80, 0x80},
    {0x81, 0x01},
    {0x81, 0x02},
    {0x81, 0x04},
    {0x81, 0x08},
    {0x81, 0x10},
    {0x81, 0x20},
    {0x81, 0x40},
    {0x81, 0x80}
};

unsigned char qsfp_int_regs[33][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0x90, 0x01},
    {0x90, 0x02},
    {0x90, 0x04},
    {0x90, 0x08},
    {0x90, 0x10},
    {0x90, 0x20},
    {0x90, 0x40},
    {0x90, 0x80},
    {0x91, 0x01},
    {0x91, 0x02},
    {0x91, 0x04},
    {0x91, 0x08},
    {0x91, 0x10},
    {0x91, 0x20},
    {0x91, 0x40},
    {0x91, 0x80},
    {0x90, 0x01},
    {0x90, 0x02},
    {0x90, 0x04},
    {0x90, 0x08},
    {0x90, 0x10},
    {0x90, 0x20},
    {0x90, 0x40},
    {0x90, 0x80},
    {0x91, 0x01},
    {0x91, 0x02},
    {0x91, 0x04},
    {0x91, 0x08},
    {0x91, 0x10},
    {0x91, 0x20},
    {0x91, 0x40},
    {0x91, 0x80}
};

unsigned char qsfp_quter_int_regs[5][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0xd0, 0x04},
    {0xd0, 0x08},
    {0xd0, 0x04},
    {0xd0, 0x08}
};

unsigned char qsfp_quter_int_mask_regs[5][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0xd1, 0x04},
    {0xd1, 0x08},
    {0xd1, 0x04},
    {0xd1, 0x08}
};

unsigned char qsfp_modprs_int_regs[5][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0xd0, 0x01},
    {0xd0, 0x02},
    {0xd0, 0x01},
    {0xd0, 0x02}
};

unsigned char qsfp_modprs_int_mask_regs[5][2] = {
    {0x00, 0x00},  //cpld offset, bit mask
    {0xd1, 0x01},
    {0xd1, 0x02},
    {0xd1, 0x01},
    {0xd1, 0x02}
};
/* end of register offset define */